論文 - 寺内 衛
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Design Guideline and Performance Prediction of 'SBB' SOI MOSFETs 査読あり
Shichio Funakoshi, Mamoru Terauchi
Technical Digest of 2000 IEEE International SOI Conference 52 - 53 2000年10月
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Characteristics of 'self-body-biased' ('SBB') SOI MOSFETs (Terauchi and Terada, 1999) have been studied in detail. Static simulations show that both the desired off-state leakage current (I/sub off/) and the on-state current (I/sub on/) ratio (I/sub on//I/sub off/) can be achieved by independently changing the impurity concentration of the 'high Na' and the 'low Na' regions of 'SBB' SOI MOSFETs. Transient simulations reveal that an inverter made of 'SBB' CMOS devices has up to 30% shorter propagation delay (/spl tau//sub pd/) at a supply voltage of 0.9 V than that for a bulk CMOS inverter under a relatively heavy load condition (load capacitance of 1 pF).
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'Self-Body- Biased' SOI MOSFET through 'Depletion Isolation Effect' 査読あり
Mamoru Terauchi, Kazuo Terada
Technical Digest of 1999 International SOI Conference 36 - 37 1999年10月
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担当区分：筆頭著者, 責任著者
A new SOI MOSFET structure utilizing a novel body potential control scheme is proposed. In its 'on' state, its body potential is electrically isolated from the external body terminal by the gate depletion layer, and is controlled automatically through the drain current and drain voltage. More than 30% improvement in current drivability is predicted.
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The Effect of Ion Implantation on the Gate Oxide Integrity of SOI Wafers 査読あり
Terauchi, Samata, Kubota, Yoshimi
Technical Digest of 1998 International SOI Conference 125 - 126 1998年10月
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担当区分：筆頭著者
The effect of ion implantation on the gate oxide integrity (GOI) of SOI wafers has been investigated. It has been found that the GOI of SOI wafers is significantly affected by ion implantation to the SOI layer before gate oxidation. SOI wafers are found to be more sensitive to metal contamination than bulk wafers because the buried oxide (BOX) layer functions as a diffusion barrier for metal contamination. The effect of the SOI-BOX interface on the gettering of metal contamination is also discussed.
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Evaluation of 0.3 micron Poly-Silicon CMOS Circuits for Intelligent Power IC Application 査読あり
Tomoko Matsudai, Mamoru Terauchi, Makoto Yoshimi, Norio Yasuhara, Yukihiro Ushiku, Akio Nakagawa
Japanese Journal of Applied Physics 37 1103 - 1106 1998年4月
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In this paper, we report on the fine device performance of a 0.3 μm gate length polysilicon complementary metal-oxide-semiconductor (CMOS). The breakdown voltage of 0.3 μm n-channel metal-oxide-semiconductor field effect transistor (NMOSFET) devices exceeds 6 V, which is higher than that of NMOSFET devices on separation by implanted oxygen (SIMOX) wafer. The drain current of a 10 μm channel width device is 540 μA, which is one-fifth of that of NMOSFET on SIMOX. The leakage current is less than 10-11 AJ/μm, when the gate voltage is below O V. The S-factor is 125 mV/dec, and the threshold voltage is 0.4 V. Therefore the ON/OFF current ratio is greater than 10^7 . A delay time of 1 ns is achieved in polysilicon NAND rings. Hence, it is ascertained that the polysilicon CMOS is applicable for the fabrication of control and protection circuits on
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'Depletion Isolation Effect' of Surrounding Gate Transistors 査読あり
Mamoru Terauchi, Akihiro Nitayama, Naoyuki Shigyo, Fumio Horiguchi
IEEE Transactions on Electron Devices 44 2303 - 2305 1997年12月
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担当区分：筆頭著者
0.5 micron以下の大きさを有する取り巻きゲート型金属酸化物半導体電界効果トランジスタ(SGT)を作成し、その電圧電流特性を研究した。シリコン柱が完全には空乏化していないSGT(例えば、0.6 micron SGT)においても、シリコン柱の下部拡散層をドレインとして用い、充分に高い電圧を印加することによって、完全空乏型SOI(Silicon-On-Insulator)デバイスに特有の理想的な電圧電流特性(例えば、室温で60 mV/dec.に迫る程の理想的なサブスレッショルド係数、基板バイアス電圧に依存しない閾値電圧など)が観測された(空乏分離効果)。
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Advantage of SOI Technology in Low Voltage ULSIs 査読あり
M. Yoshimi, S. Kawanaka, T. Yamada, M. Terauchi, T. Shino, T. Fuse, Y. Oowaki, S. Watanabe
SPIE Microelectronic Device Technology 3212 178 - 187 1997年10月
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Low power advantage of SOI (silicon-on-insulator) technology is presented. A 0.5 V operation ALU is demonstrated by employing a gate-to-body connected structure. From the viewpoint of reliability in process integration, origin of a leakage current between source and drain is investigated in detail. The performance advantage of fabricated SOI ALUs over bulk devices as well as issues to be overcome are discussed.
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An Ultra Low Voltage SOI CMOS Pass-Gate Logic 査読あり
Fuse, Oowaki, Terauchi, Watanabe, Yoshimi, Oouchi, Matsunaga
IEICE Transactions on Electronics E80-C 472 - 477 1997年10月
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An ultra low voltage CMOS pass-gate logic using body-bias controlled SOI MOSFETs has been developed. The logic is composed of gate-body connected SOI pass-gates and a CMOS buffer with the body-bias controlled by the complementary double-rail input. The full-adder using the proposed logic improved the lowest operation voltage by 27%, compared with the SOI CPL (Complementary Pass-Gate Logic). For a 16 16 bit multiplier, the power-delay product achieved 70 pJ (including 50 pF I/O) at 0.5 V power supply, which was more than 1 order of magnitude improvement over the bulk CPL.
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Evaluation of 0.3 micron Poly-Silicon CMOS Circuits for Intelligent Power IC Application 査読あり
Tomoko Matsudai, Mamoru Terauchi, Makoto Yoshimi, Norio Yasuhara, Yukihiro Ushiku, Akio Nakagawa
Extended Abstracts of the 1997 International Conference on Solid-State Devices and Materials 378 - 379 1997年9月
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Yoshimi, Terauchi, Nishiyama, Arisumi, Matsuzawa, Shigyo, Takeno, Tomita, Suzuki, Ushiku, Tango
IEEE Transactions on Electron Devices 44 423 - 430 1997年3月
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SOI MOSFETにおける基板浮遊効果を抑制するバンドギャップエンジニアリングの提唱とSiGeソース/ドレイン構造による実証。
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A 0.5V 200Mhz 1-stage 32b ALU using a body bias controlled SOI Pass-Gate Logic 査読あり
Fuse, Oowaki, Yamada, Kamoshida, Oota, Shino, Kawanaka, Terauchi, Yoshida, Matsubara, et al.
Technical Digest of 1997 IEEE International Solid-State Circuits Conference 286 - 287 1997年2月
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SOI CMOS with gate-body connection (DTMOS) and body bias controlled SOI pass-gate logic (BCSOI pass-gate) take advantage of individually isolated SOI device active area and reduce threshold voltage by controlling each device body bias. Hence, they enjoy higher speed than circuits based on fixed low threshold voltage. The direct body bias control used in previous work suffers from leakage current at supply voltage higher than 0.8V due to drain-body junction leakage. A practical circuit technology that offers the highest speed, lowest operation voltage and stable operation under wide supply voltage demonstrates performance with an ALU macro using this technology.
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The Impact of the Floating-Body Effect Suppression on SOI Integrated Circuits 査読あり
Mamoru Terauchi, Akira Nishiyama, Tomohisa Mizuno, Makoto Yoshimi, Shigeyoshi Watanabe
Technical Digest of 1996 IEEE International Electron Devices Meeting 855 - 858 1996年12月
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担当区分：筆頭著者
The bandgap engineering technique suppresses not only anomalies in the DC transfer characteristics of SOI CMOS circuits but also characteristics fluctuations of SOI MOSFETs. It is experimentally verified that the floating-body effects in 8 k SOI MOSFETs in 0.7 mm/sup 2/ wafer area cannot be controlled completely with a conventional fabrication technique. Thus it is concluded that the suppression of the floating body effects is essential to fabricate actual LSIs utilizing SOI devices.
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Analysis of Floating-Body-Induced Leakage Current in 0.15 micron SOI DRAM 査読あり
Mamoru Terauchi, Makoto Yoshimi
Technical Digest of 1996 IEEE International SOI Conference 138 - 139 1996年10月
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担当区分：筆頭著者
Summary form only given. Degradation of the dynamic retention time in SOI DRAMs is a critical issue in the application of SOI technology to memory devices. One possible degradation mode related with the floating-body effect occurs in a non-selected memory cell storing "1" due to a transient lowering of the threshold voltage (Vth) of the transistor associated with a voltage drop of a data line from a precharge level to 0 V. It was reported that this dynamism can induce a leakage current as high as several mA at low voltage regions. In this paper, the possibility of this degradation mode in a 0.15 /spl mu/m SOI DRAM cell is analyzed in detail considering various device parameters and the design guideline to avoid the degradation is described.
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Reduction of the Floating-Body Effect in SOI-MOSFETs by the Bandgap Engineering Method 査読あり
Yoshimi, NIshiyama, Arisumi, Terauchi, Matsuzawa, Shigyo
Proceedings of 7th International Symposium on Silicon-On-Insulator Technology and Devices 231 - 236 1996年10月
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Advantages of Low Voltage Applications and Issues to be Solved in SOI Technology 査読あり
Yoshimi, Terauchi, Nishiyama, Numano, Kubota, Watanabe, Tango
Technical Digest of 1996 IEEE International SOI Conference 4 - 5 1996年10月
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With low voltage applications as the main objective, SOI technology has made rapid and substantial progress in recent years. This paper describes the current status of SOI technology with emphasis on analysis of dynamic retention characteristics in low voltage DRAMs, countermeasures regarding the floating-body effect in low voltage region, and reliability issues in state-of-the-art SOI substrate technology.
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Analysis of Si-Ge Source Structure in 0.15 micron SOI MOSFETs Using Two Dimensional Device Simulation 査読あり
Arisumi, Matsuzawa, Shigyo, Terauchi, Nishiyama, Yoshimi
Japanese Journal of Applied Physics 35 992 - 995 1996年4月
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We describe the technological potential of the bandgap engineering technique involving a Si-Ge source structure in a fully-depleted SOI MOSFET to suppress the'floating-body effect. The Si-Ge layer fabricated in the source region acts as an absorber for excess holes in the channel region. The detailed .mechanism as well as the structure dependence in SOI MOSFETs with a gate length of 0.15 μm have been studied using a two-dimensional device simulation. It has been found that the imprpvement in BVds is strongly dependent on the lateral position of the Si-Ge layer relative to the source-to-channel pn junction. It is further predicted that encroachment of the Si-Ge layer into the channel region achieves the maximum BVds improvement. The BVds improvement is predicted to reach 1.5 V if it proves possible to lower the energy barrier at the pn junction in the case where tlEg = 0.2 eV.
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Formation of SiGe Source/Drain Using Ge Implantation for Floating-Body Effect Resistant SOI MOSFETs 査読あり
Nishiyama, Arisumi, Terauchi, Takeno, Suzuki, Takakuwa, Yoshimi
Japanese Journal of Applied Physics 35 954 - 959 1996年4月
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SiGe was formed by Ge implantation into silicon on insulator (SOI) substrates with the dosage range from 0.5 to 3 X 1016 cm-2 and subsequent annealing in N2 . The implantation dosage dependence of the crystalline quality, bandgap and sheet resistance of the SiGe layers are investigated. The implantation damage for Ge dosage up to 1 X 1016 cm-2 can be removed at a temperature as low as 700°C. A SiGe crystalline network is formed by the annealing at the same time. With a Ge dosage of 1 x 1016 cm-2 or more, bandgap narrowing of the SiGe layer was detected. Sheet resistances of SiGe N+ and p+ layers gradually increase for higher Ge dosage. SOI MOSFET characteristics in terms of the floating-body effect with the SiGe source/drain layers are presented. The bandgap narrowing suppresses the floating-body effect of fully depleted SOI MOSFETs, while maintaining the reverse leakage current of the p-n junction between the source/drain and channel at a low level.
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0.5V SOI CMOS Pass-Gate Logic 査読あり
Fuse, Oowaki, Terauchi, Watanabe, Yoshimi, Oouchi, Matsunaga
Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference 88 - 89 1996年2月
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Demand for low-power ULSIs for mobile electronic equipment is increasing rapidly. To reduce power consumption, lower operating voltage and minimized device size (or count) is essential. To lower the actual threshold voltage and lower the operation voltage, SOI MOSFET with gate-body connection is proposed. However, the circuit architecture that affords the maximum advantage of the body controlled SOI MOSFET has not yet been reported. The SOI CMOS pass-gate logic described here offers the lowest operation voltage and reduced transistor dimensions. In this logic the body of the SOI pass-gate is connected to the input signal given to the gate. Low threshold voltage for the onstate pass-gate and high threshold voltage for the off-state passgate is realized, and the increase in the threshold voltage due to the body-effect is suppressed. Two types of buffer suitable for SOI pass-gate logic are examined.
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Bandgap Engineering Technology for Suppressing the Floating-Body-Effect in 0.15 mm SOI-MOSFET 査読あり
Yoshimi, Nishiyama, Terauchi, Arisumi, Murakoshi, Ushiku, Takeno, Suzuki
Technical Digest of 1995 IEEE International SOI Conference 80 - 81 1995年10月
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The substrate floating effect is the most fundamental problem in SOI-MOSFETs. Conventional countermeasures, such as body-contact, LDD structure are accompanied by area penalty, Id degradation and other drawbacks. To suppress this effect, we have proposed the bandgap engineering method, in which a narrow bandgap material is formed in the source region. In this paper, an ideal structure for the bandgap engineering is discussed and actually achievable performance is estimated based on simulations and experiments for 0.15 /spl mu/m SOI-MOSFETs.
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Formation of SiGe Source/Drain Using Ge Implantation for Floating-Body Effect Resistant SOI MOSFETs 査読あり
Nishiyama, Arisumi, Terauchi, Yoshimi, Takeno, Suzuki
Extended Abstracts of the 1995 International Conference on Solid State Devices and Materials 545 - 547 1995年9月
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Analysis of Si-Ge Source Structure in 0.15 micron SOI MOSFETs Using Two-Dimensional Device Simulation 査読あり
Arisumi, Matsuzawa, Shigyo, Terauchi, Nishiyama, Yoshimi
Extended Abstracts of the 1995 International Conference on Solid State Devices and Materials 860 - 862 1995年9月
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