論文 - 寺内 衛
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ソフトウエアによるDRAM支配－DRAM価格トレンドに関する一考察－ 査読あり
寺内 衛
政経研究 ( 73 ) 73 - 80 1999年11月
単著
担当区分：筆頭著者
ダイナミックランダムアクセスメモリ（DRAM）の需給は、パーソナルコンピュータ（ＰＣ）に搭載されるDRAMの個数で決定される。３２ビットＰＣの普及に伴い、ＰＣの主記憶容量は、アプリケーション／ＯＳといったソフトウエアによって決定されるようになった。近年では、Microsoft社製Windows系列の変化に合わせてＰＣの主記憶容量は着実に増大（３年で２倍）したが、過去のトレンドに盲従したDRAM高集積化のスピード（３年で４倍）の方が早かったため、大幅な価格下落を招いた。今後、DRAMメーカーがエンドユーザに対してDRAMの新たな使用方法をこれまで以上にわかりやすく提示できない限り、DRAM使用量の増加をソフトウエアメーカーに依存し続ける体質は変わらず、DRAM事業収益性の自立的な向上は望めないであろう。
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A Test Circuit for Evaluating Characteristics Mismatch in Metal-Oxide- Semiconductor Field- Effect Transistor Pairs by Estimating Conductance Variation through Voltage Measurement 査読あり
Mamoru Terauchi, Kazuo Terada
Japanese Journal of Applied Physics 47 4480 - 4486 2008年6月
共著
担当区分：筆頭著者, 責任著者
A procedure is described for evaluating characteristics mismatch in a pair of metal–oxide–semiconductor field-effect transistors (MOSFETs), which are nominally designed to be identical. This procedure is based on conductance variation estimation through voltage measurement. By measuring the gate voltage dependence of the voltage of the middle point of a MOSFET pair connected in series, various pieces of information on difference in characteristics (e.g., channel width difference and threshold voltage difference) in the MOSFET pair can be extracted. The applicability of the proposed procedure to fabrication process monitoring is also described and the principle of a suitable test circuit structure is illustrated.
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Impact of Substrate Bias on Fixed-Pattern- Noise in Active Pixel Sensor Cells 査読あり
Mamoru Terauchi
Japanese Journal of Applied Physics 46 7303 - 7305 2007年11月
単著
担当区分：筆頭著者
The study investigated the impact of substrate (body) bias on fixed pattern noise (FPN) in Active Pixel Sensors (APS). By measuring a test device that serially connects two metal-oxide-semiconductor field-effect transistors (MOSFETs) placed within the same well region, it was revealed that the finite substrate bias, which is inevitable in conventional APS cell circuits using traditional methods, degrades the characteristic fluctuations of the source follower amplifier included in the APS cell. This results in FPN that cannot be improved by conventional correction methods such as correlated double sampling. Furthermore, it was shown that the current-voltage characteristics of the logarithmic conversion circuit, achieved by connecting the gate and drain of the MOSFET, are also affected by the substrate bias, leading to increased characteristic variations compared to when the substrate bias is zero.
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Feasibility Study of a Novel Four Transistor Silicon-on-Insulator Static Random Access Memory Cell Utilizing Partial Trench Isolation 査読あり
Mamoru Terauchi
Japanese Journal of Applied Physics 46 5136 - 5138 2007年8月
単著
担当区分：筆頭著者
0.5 V動作を志向し、薄膜SOI(Silicon-On- Insulator)基板上に作成した四つの薄膜SOI金属酸化物半導体電界効果トランジスタ(MOSFET)からなる新規スタティックランダムアクセスメモリ(SRAM)を提案する。本研究に係る新規SRAMにおいては、対向接続されたトランジスタ対のボディ領域が負荷抵抗として利用される。各SRAMセルをワード線に接続しているトランスファーMOSFETはダイナミックスレッショルドMOSFET(DTMOS)である。部分トレンチ分離法を用いることにより、本研究に係るSRAMセルにおいては、ボディコンタクトを実現するための特殊なゲート電極形状が廃されている。回路解析機能を有するデバイスシミュレータを利用することによって、本研究において提案されたSRAMセルが0.5 Vという低電圧で正常に動作することが明らかになった。
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Impact of Forward Substrate Bias on Threshold Voltage Fluctuation in Metal- Oxide-Semiconductor Field-Effect Transistors 査読あり
Mamoru Terauchi
Japanese Journal of Applied Physics 46 4105 - 4107 2007年7月
単著
担当区分：筆頭著者
The impact of forward body (substrate) bias voltage on the threshold voltage (Vth) of metal-oxide-semiconductor field-effect transistors (MOSFETs) and its dependence on device parameters (such as gate length, substrate impurity concentration, and gate oxide thickness) were investigated using a charge-sharing model. It was shown that applying a forward body bias voltage of 0.5 V can suppress Vth fluctuations by up to 20% in devices with a gate length of 100 nm or less, and reduce the sensitivity of Vth to device parameters. Additionally, experimental results demonstrating the Vth fluctuation suppression effect due to forward body bias voltage were presented.
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A Wide-Dynamic Range Photodiode-Type Active Pixel Sensor Cell with Seamlessly Combined Logarithmic-Linear- Logarithmic Response 査読あり
Atsushi Hamasaki, Mamoru Terauchi, Kenju Horii
Japanese Journal of Applied Physics 46 4051 - 4054 2007年7月
共著
A photodiode (PD) type active pixel sensor (APS) cell with a continuous log-linear-log response over a wide dynamic range is proposed for the first time, and its operation is confirmed through circuit simulation. The proposed APS cell has two additional MOSFETs connected in parallel to the reset MOSFET (metal-oxide-semiconductor field-effect transistor) compared to the conventional 3-transistor (3Tr) type PD APS cell. By utilizing the previously proposed operating method, it is shown that the newly proposed 5Tr type PD APS cell exhibits a continuous log-linear-log response.
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Temperature Dependence of the Subthreshold Characteristics of Dynamic Threshold Metal-Oxide- Semiconductor Field-Effect Transistors and Its Application to an Absolute-Temperature Sensing Scheme for Low-Voltage Operation 査読あり
Mamoru Terauchi
Japanese Journal of Applied Physics 46 4102 - 4104 2007年7月
単著
担当区分：筆頭著者
A method for detecting absolute temperature based on the temperature dependence of the voltage-current characteristics of dynamic threshold metal-oxide-semiconductor field-effect transistors (DTMOS) in the subthreshold region is proposed. This proposed method does not require voltages greater than 0.5 V or initial calibration. While this method is well-suited for SOI (Silicon-On-Insulator) circuits based on SOI technology using SOI substrates, it can also be easily applied to conventional bulk MOS devices. Experimental results of absolute temperature measurement using bulk MOS devices are also presented.
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連続的に切り替わる線形－対数応答特性を有するフォトダイオード型4-Trアクティブピクセルセンサセル 査読あり
浜崎 淳、寺内 衛、堀居賢樹
映像情報メディア学会誌 60 ( 7 ) 1111 - 1113 2006年7月
共著
連続的に切り替わる線形－対数応答特性を有するフォトダイオード型4-Trアクティブピクセルセンサセルの提案とシミュレーションによる性能予測。適切に選択したバイアス電圧でリセットトランジスタを弱反転状態にバイアスすることにより、線型応答→対数応答へ自動的に特性を変化させられることを見いだした。
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A Novel Operation Scheme for Realizing Combined Linear- Logarithmic Response in Photodiode-Type Active Pixel Sensor Cells 査読あり
Atsushi Hamasaki, Mamoru Terauchi, Kenju Horii
Japanese Journal of Applied Physics 45 3326 - 3329 2006年4月
共著
We propose a photodiode (PD) type active pixel sensor (APS) cell with a continuous linear-logarithmic response. In a 3-transistor (3Tr) type PD APS cell, by appropriately selecting the bias voltage to operate the reset transistor in the weak inversion region, we have shown through simulation that the conventional 3Tr PD APS cell exhibits a continuous linear-logarithmic response. We also discuss methods to expand the dynamic range in the linear response region of conventional APS cells
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A Novel Operation Scheme for Realizing Combined Linear- Logarithmic Response in Photodiode- Type Active Pixel Sensor Cells 査読あり
Atsushi Hamasaki, Mamoru Terauchi, Kenju Horii
Extended Abstracts of the 2005 International Conference on Solid-State Devices and Materials 666 - 667 2005年9月
共著
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Selectable Logarithmic/Linear Response Active Pixel Sensor Cell with Reduced Fixed-Pattern- Noise Based on Dynamic Threshold MOS Operation 査読あり
Mamoru Terauchi, Atsushi Hamasaki, Arinori Suketa
Japanese Journal of Applied Physics 44 2347 - 2350 2005年4月
共著
担当区分：筆頭著者
A new active pixel sensor (APS) cell is proposed that has lower fixed pattern noise (FPN) compared to conventional devices and can select between linear and logarithmic responses. This APS cell consists of four dynamic threshold metal-oxide-semiconductor field-effect transistors (DTMOS). DTMOS inherently has smaller characteristic fluctuations compared to conventional MOSFETs, which can be explained by the charge-sharing model. Therefore, the proposed APS cell exhibits lower FPN in the logarithmic response region compared to conventional logarithmic response APS cells, even without an external noise reduction circuit. The FPN reduction achieved by the proposed APS cell was confirmed by measuring a test circuit that mimics the readout circuit of a real device.
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A Selectable Logarithmic / Linear Response Active Pixel Sensor Cell with Reduced Fixed-Pattern- Noise Based on DTMOS Operation 査読あり
Mamoru Terauchi, Atsushi Hamasaki, Arinori Suketa
Extended Abstracts of the 2004 International Conference on Solid-State Devices and Materials 504 - 505 2004年9月
共著
担当区分：筆頭著者
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SOI SRAM / DRAM Cells for 0.5 V Operation 査読あり
Mamoru Terauchi
Japanese Journal of Applied Physics 43 2160 - 2165 2004年4月
単著
担当区分：筆頭著者
Described are a 4-transistor static random access memory (4T SRAM) and a dynamic random access memory (DRAM) gain cell, both created using SOI (Silicon-On-Insulator) substrates and capable of low-voltage operation. Both cells actively utilize the body regions of partially depleted SOI metal-oxide-semiconductor field-effect transistors (MOSFETs). In the 4T SRAM cell, the body region of an SOI MOSFET with an H-shaped gate electrode is used as the load resistor for the proposed SRAM cell's inverter pair, and its resistance value can be controlled independently of the MOSFET's threshold voltage. Simulation results demonstrated the stable operation of the proposed 4T SRAM at a power supply voltage of 0.5 V. The SOI DRAM gain cell consists of a p-channel junction field-effect transistor (JFET) and an n-channel MOSFET, with the MOSFET's source diffusion layer also serving as the JFET's gate diffusion layer. The signal charge is stored in the gate junction capacitance of this JFET, modulating its source-drain conductance. Simulation results confirmed that the proposed SOI DRAM gain cell operates normally at a power supply voltage of 0.5 V.
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A Novel Photodiode- Type Active Pixel Sensor Utilizing DTMOS with Reduced Fixed-Pattern Noise 査読あり
Mamoru Terauchi
Technical Digest of 2003 IEEE International SOI Conference 57 - 58 2003年10月
単著
担当区分：筆頭著者
A novel active pixel sensor with reduced fixed-pattern-noise is proposed and its effectiveness is experimentally verified. Smaller characteristics fluctuation in threshold voltage and drain conductance of DTMOS than that of bulk counterpart considerably reduces fixed-pattern-noise of the proposed photodiode-type APS.
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SOI SRAM / DRAM Cells for 0.5 Volt Operation 査読あり
Mamoru Terauchi
Extended Abstracts of the 2003 International Conference on Solid-State Devices and Materials 620 - 621 2003年9月
単著
担当区分：筆頭著者
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A 'Self-Body- Biased' SOI MOSFET: A Novel Body-Voltage- Controlled SOI MOSFET for Low Voltage Applications 査読あり
Mamoru Terauchi, Shichio Funakoshi
Japanese Journal of Applied Physics 42 2014 - 2019 2003年4月
共著
担当区分：筆頭著者
A new body potential control scheme for SOI (Silicon-On-Insulator) metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed, and its characteristics are investigated through simulation. In the "on" state, the body potential is electrically isolated from the external body terminal by the gate depletion layer and is automatically controlled by the drain voltage and drain current. This new structure is predicted by simulation to achieve over 30% increase in current drive capability compared to an equivalent MOSFET using a bulk substrate. Mixed-mode simulation revealed that a CMOS inverter composed of the proposed device has a shorter propagation delay compared to a bulk CMOS inverter. Furthermore, simulation showed that the proposed device does not exhibit the history effect on propagation delay that is characteristic of conventional partially depleted SOI devices. This is because, in the "off" state, the proposed device is equivalent to a conventional body-tied partially depleted SOI device, allowing excess majority carriers, the main cause of the history effect, to be swept out from the body terminal each time the device turns off.
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A Logic-Process- Compatible SOI DRAM Gain Cell Operating at 0.5 Volt 査読あり
Mamoru Terauchi
Technical Digest of 2002 IEEE International SOI Conference 86 - 87 2002年10月
単著
担当区分：筆頭著者
A novel SOI DRAM gain cell operating at 0.5 V is proposed. It consists of a p-channel JFET and an n-channel MOSFET, whose source diffusion functions as gate diffusion of the JFET as well. Signal charge is stored in the gate diffusion capacitance of the JFET, leading to the modulation in its source-drain conductance. Mixed-mode simulation with the use of a device simulator reveals that the proposed SOI DRAM gain cell is able to operate properly under supply voltage as low as 0.5 V.
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'History Effect'- Free Operation of 'SBB' SOI MOSFETs 査読あり
Mamoru Terauchi, Shichio Funakoshi
Extended Abstract of 2002 International Conference on Solid-State Devices and Materials 596 - 597 2002年9月
共著
担当区分：筆頭著者
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Threshold Voltage Fluctuation Analysis in Dynamic Threshold MOSFET Based on Charge-Sharing 査読あり
Mamoru Terauchi
Technical Digest of 2001 IEEE International SOI Conference 53 - 54 2001年10月
単著
担当区分：筆頭著者
Threshold voltage (V/sub th/) fluctuation in Dynamic Threshold MOSFET (DTMOS) is analyzed based on a charge-sharing model. It has been revealed that the gate depiction layer width in DTMOS devices is smaller than that in body-tied partially-depleted SOI MOSFETs (PDSOI) or bulk MOSFET in normal conditions, leading to smaller V/sub th/ fluctuation in DTMOS (/spl sigma//sub Vth//sup DT/) due to impurity number fluctuation in the gate depiction layer. Vth sensitivity on both impurity concentration (N/sub a/) and gate oxide thickness (T/sub ox/) is also reduced in DTMOS.
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A Novel 4T SRAM Cell Utilizing 'Self-Body- Biased' SOI MOSFET Structure Operating at 0.5 Volt 査読あり
Mamoru Terauchi
Technical Digest of 2000 IEEE International SOI Conference 108 - 109 2000年10月
単著
担当区分：筆頭著者
A novel 4T SRAM cell utilizing the 'self-body-biased' ('SBB') SOI MOSFET structure (Terauchi and Terada, Proc. IEEE Int. SOI Conf., p. 36, 1999) is proposed. The body region of an SOI MOSFET with an 'H-shaped' gate electrode is used as a resistor in the inverter pair of the SRAM cell. The resistance of the body region is controlled by the low impurity concentration region beneath the auxiliary gate electrode and its geometry, independently from the threshold voltage of the MOSFET. Device simulation reveals the stable operation of the proposed SRAM cell under supply voltage of as low as 0.5 V.