Papers - TERAUCHI Mamoru
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'Self-Body- Biased' SOI MOSFET through 'Depletion Isolation Effect' Reviewed
Mamoru Terauchi, Kazuo Terada
Technical Digest of 1999 International SOI Conference 36 - 37 1999.10
Joint Work
Authorship:Lead author
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The Effect of Ion Implantation on the Gate Oxide Integrity of SOI Wafers Reviewed
Terauchi, Samata, Kubota, Yoshimi
Technical Digest of 1998 International SOI Conference 125 - 126 1998.10
Joint Work
Authorship:Lead author
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Evaluation of 0.3 micron Poly-Silicon CMOS Circuits for Intelligent Power IC Application Reviewed
Tomoko Matsudai, Mamoru Terauchi, Makoto Yoshimi, Norio Yasuhara, Yukihiro Ushiku, Akio Nakagawa
Japanese Journal of Applied Physics 37 1103 - 1106 1998.4
Joint Work
インテリジェントパワーIC向け0.3ミクロンポリシリコン薄膜トランジスタによるCMOS回路の提案とその実証。0.3ミクロンポリシリコン薄膜トランジスタを試作し、その電圧電流特性を測定した。
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'Depletion Isolation Effect' of Surrounding Gate Transistors Reviewed
Mamoru Terauchi, Akihiro Nitayama, Naoyuki Shigyo, Fumio Horiguchi
IEEE Transactions on Electron Devices 44 2303 - 2305 1997.12
Joint Work
Authorship:Lead author
0.5 micron以下の大きさを有する取り巻きゲート型金属酸化物半導体電界効果トランジスタ(SGT)を作成し、その電圧電流特性を研究した。シリコン柱が完全には空乏化していないSGT(例えば、0.6 micron SGT)においても、シリコン柱の下部拡散層をドレインとして用い、充分に高い電圧を印加することによって、完全空乏型SOI(Silicon-On-Insulator)デバイスに特有の理想的な電圧電流特性(例えば、室温で60 mV/dec.に迫る程の理想的なサブスレッショルド係数、基板バイアス電圧に依存しない閾値電圧など)が観測された(空乏分離効果)。
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Advantage of SOI Technology in Low Voltage ULSIs Reviewed
M. Yoshimi, S. Kawanaka, T. Yamada, M. Terauchi, T. Shino, T. Fuse, Y. Oowaki, S. Watanabe
SPIE Microelectronic Device Technology 3212 178 - 187 1997.10
Joint Work
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An Ultra Low Voltage SOI CMOS Pass-Gate Logic Reviewed
Fuse, Oowaki, Terauchi, Watanabe, Yoshimi, Oouchi, Matsunaga
IEICE Transactions on Electronics E80-C 472 - 477 1997.10
Joint Work
SOI MOSFETによる超低電圧動作パスゲート論理回路の提案とその実証。素子試作を行ない、0.5 V動作を確認した。
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Evaluation of 0.3 mm Poly-Silicon CMOS Circuits for Intelligent Power IC Application Reviewed
Tomoko Matsudai, Mamoru Terauchi, Makoto Yoshimi, Norio Yasuhara, Yukihiro Ushiku, Akio Nakagawa
Extended Abstracts of the 1997 International Conference on Solid-State Devices and Materials 378 - 379 1997.9
Joint Work
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Suppression of the Floating-Body Effect in SOI MOSFETs by Bandgap Engineering Method Using a Si1-xGex Source Structure Reviewed
Yoshimi, Terauchi, Nishiyama, Arisumi, Matsuzawa, Shigyo, Takeno, Tomita, Suzuki, Ushiku, Tango
IEEE Transactions on Electron Devices 44 423 - 430 1997.3
Joint Work
SOI MOSFETにおける基板浮遊効果を抑制するバンドギャップエンジニアリングの提唱とSiGeソース/ドレイン構造による実証。
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A 0.5V 200Mhz 1-stage 32b ALU using a body bias controlled SOI Pass-Gate Logic Reviewed
Fuse, Oowaki, Yamada, Kamoshida, Oota, Shino, Kawanaka, Terauchi, Yoshida, Matsubara, et al.
Technical Digest of 1997 IEEE International Solid-State Circuits Conference 286 - 287 1997.2
Joint Work
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The Impact of the Floating-Body Effect Suppression on SOI Integrated Circuits Reviewed
Mamoru Terauchi, Akira Nishiyama, Tomohisa Mizuno, Makoto Yoshimi, Shigeyoshi Watanabe
Technical Digest of 1996 IEEE International Electron Devices Meeting 855 - 858 1996.12
Joint Work
Authorship:Lead author
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Analysis of Floating-Body-Induced Leakage Current in 0.15 micron SOI DRAM Reviewed
Mamoru Terauchi, Makoto Yoshimi
Technical Digest of 1996 IEEE International SOI Conference 138 - 139 1996.10
Joint Work
Authorship:Lead author
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Reduction of the Floating-Body Effect in SOI-MOSFETs by the Bandgap Engineering Method Reviewed
Yoshimi, NIshiyama, Arisumi, Terauchi, Matsuzawa, Shigyo
Proceedings of 7th International Symposium on Silicon-On-Insulator Technology and Devices 231 - 236 1996.10
Joint Work
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Advantages of Low Voltage Applications and Issues to be Solved in SOI Technology Reviewed
Yoshimi, Terauchi, Nishiyama, Numano, Kubota, Watanabe, Tango
Technical Digest of 1996 IEEE International SOI Conference 4 - 5 1996.10
Joint Work
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Analysis of Si-Ge Source Structure in 0.15 micron SOI MOSFETs Using Two Dimensional Device Simulation Reviewed
Arisumi, Matsuzawa, Shigyo, Terauchi, Nishiyama, Yoshimi
Japanese Journal of Applied Physics 35 992 - 995 1996.4
Joint Work
SOI MOSFETにおいて基板浮遊効果を抑制するためのSiGeソース/ドレイン構造に関するシミュレーションによる考察。
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Formation of SiGe Source/Drain Using Ge Implantation for Floating-Body Effect Resistant SOI MOSFETs Reviewed
Nishiyama, Arisumi, Terauchi, Takeno, Suzuki, Takakuwa, Yoshimi
Japanese Journal of Applied Physics 35 954 - 959 1996.4
Joint Work
SOI MOSFETにおいて基板浮遊効果を抑制するためのSiGeソース/ドレイン形成に関する実験的検証。
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0.5V SOI CMOS Pass-Gate Logic Reviewed
Fuse, Oowaki, Terauchi, Watanabe, Yoshimi, Oouchi, Matsunaga
Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference 88 - 89 1996.2
Joint Work
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Bandgap Engineering Technology for Suppressing the Floating-Body-Effect in 0.15 mm SOI-MOSFET Reviewed
Yoshimi, Nishiyama, Terauchi, Arisumi, Murakoshi, Ushiku, Takeno, Suzuki
Technical Digest of 1995 IEEE International SOI Conference 80 - 81 1995.12
Joint Work
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Formation of SiGe Source/Drain Using Ge Implantation for Floating-Body Effect Resistant SOI MOSFETs Reviewed
Nishiyama, Arisumi, Terauchi, Yoshimi, Takeno, Suzuki
Extended Abstracts of the 1995 International Conference on Solid State Devices and Materials 545 - 547 1995.9
Joint Work
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Analysis of Si-Ge Source Structure in 0.15 micron SOI MOSFETs Using Two-Dimensional Device Simulation Reviewed
Arisumi, Matsuzawa, Shigyo, Terauchi, Nishiyama, Yoshimi
Extended Abstracts of the 1995 International Conference on Solid State Devices and Materials 860 - 862 1995.9
Joint Work
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Suppression of the Floating-Body Effects in SOI MOSFETs by Bandgap Engineering Reviewed
Mamoru Terauchi, Makoto Yoshimi, Atsushi Murakoshi, Yukihiro Ushiku
Digest of Technical Papers, 1995 Symposium on VLSI Technology 35 - 36 1995.6
Joint Work
Authorship:Lead author